{"name":"haskellPackages.hsverilog","version":"0.1.0","summary":"Synthesizable Verilog DSL supporting for multiple clock and reset","systems":{"aarch64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"haskellPackages.hsverilog"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/822w8mdj24ncdvawq4lsqn40r2n64m9z-hsverilog-0.1.0","default":true},{"name":"doc","path":"/nix/store/aa2650sxj0bbqwsmclkydjvwdmfgn1si-hsverilog-0.1.0-doc"}]},"aarch64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"haskellPackages.hsverilog"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/fjlmddm2c8vlydlmm3qnf4q2vip4rmhl-hsverilog-0.1.0","default":true},{"name":"doc","path":"/nix/store/1467rbcjp96ag98ikzpvmvbikpw1dq2w-hsverilog-0.1.0-doc"}]},"x86_64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"3d46470bb3030020f7e1361f33514854f5bfa86d"},"attr_path":"haskellPackages.hsverilog"},"last_updated":"2026-06-27T07:37:20Z","outputs":[{"name":"out","path":"/nix/store/pv5553vnz4k8hkk2xhs40javwm2281sa-hsverilog-0.1.0","default":true},{"name":"doc","path":"/nix/store/nnlv5girnx0zk99a7wzahg7n96b90zbr-hsverilog-0.1.0-doc"}]},"x86_64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"haskellPackages.hsverilog"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/pp2wpc6dhhyy65bkk65wga02lbmmdz1x-hsverilog-0.1.0","default":true},{"name":"doc","path":"/nix/store/wzgf6r9sq5vqw3wrsjvwxbjlr4nvbgns-hsverilog-0.1.0-doc"}]}}}