{"name":"vhd2vl","version":"0-unstable-2026-02-16","summary":"VHDL to Verilog converter","systems":{"aarch64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"5adc50831c259f87faeb09ddf930d43597197473"},"attr_path":"vhd2vl"},"last_updated":"2026-10-20T14:23:57Z","outputs":[{"name":"out","path":"/nix/store/iqn2njz8bxsyjyiql9dclvfgcagc8vl1-vhd2vl-0-unstable-2026-02-16","default":true}]},"aarch64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"5adc50831c259f87faeb09ddf930d43597197473"},"attr_path":"vhd2vl"},"last_updated":"2026-10-20T14:23:57Z","outputs":[{"name":"out","path":"/nix/store/ah4l8rhrx2788als70azq69yr16qh31l-vhd2vl-0-unstable-2026-02-16","default":true}]},"x86_64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"5adc50831c259f87faeb09ddf930d43597197473"},"attr_path":"vhd2vl"},"last_updated":"2026-10-20T14:23:57Z","outputs":[{"name":"out","path":"/nix/store/f41cvd6npa86gkrwhsmznmlwazql27ww-vhd2vl-0-unstable-2026-02-16","default":true}]}}}