{"name":"vhd2vl","version":"2022-12-26","summary":"VHDL to Verilog converter","systems":{"aarch64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"a421ac6595024edcfbb1ef950a3712b89161c359"},"attr_path":"vhd2vl"},"last_updated":"2025-07-13T22:45:35Z","outputs":[{"name":"out","path":"/nix/store/alrijzdrv510ldkflhvvx837md1im2v4-vhd2vl-unstable-2022-12-26","default":true}]},"aarch64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"a421ac6595024edcfbb1ef950a3712b89161c359"},"attr_path":"vhd2vl"},"last_updated":"2025-07-13T22:45:35Z","outputs":[{"name":"out","path":"/nix/store/50g3r7sss3608iq3cvp7hn1lwz2w74id-vhd2vl-unstable-2022-12-26","default":true}]},"x86_64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"a421ac6595024edcfbb1ef950a3712b89161c359"},"attr_path":"vhd2vl"},"last_updated":"2025-07-13T22:45:35Z","outputs":[{"name":"out","path":"/nix/store/472l34ilfaq3bx4jfamaj5nd6bwb9a7m-vhd2vl-unstable-2022-12-26","default":true}]},"x86_64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"a421ac6595024edcfbb1ef950a3712b89161c359"},"attr_path":"vhd2vl"},"last_updated":"2025-07-13T22:45:35Z","outputs":[{"name":"out","path":"/nix/store/zkns7x25q5sylj474q16m3d053mvj62j-vhd2vl-unstable-2022-12-26","default":true}]}}}