{"name":"vhd2vl","version":"0-unstable-2026-02-16","summary":"VHDL to Verilog converter","systems":{"aarch64-darwin":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"vhd2vl"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/nf5ff5mkpy2rlh0kyhgm4h3w5mvla7gs-vhd2vl-0-unstable-2026-02-16","default":true}]},"aarch64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"vhd2vl"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/aq3g0y7nl1z73ia2k13f9sfy2div7rk5-vhd2vl-0-unstable-2026-02-16","default":true}]},"x86_64-linux":{"flake_installable":{"ref":{"type":"github","owner":"NixOS","repo":"nixpkgs","rev":"c9fe7d12cd78d1adcd12dd15e24432dde5b155a0"},"attr_path":"vhd2vl"},"last_updated":"2026-09-30T11:58:46Z","outputs":[{"name":"out","path":"/nix/store/hm2gi8ayzj84ys6x7jbbwxw10pfhp10w-vhd2vl-0-unstable-2026-02-16","default":true}]}}}